Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction Scheme

Authors

  • A. T. A. Kishore Kumar Assistant Professor, Department of ECE, KMM Institute of Technology & Science, Andhra Pradesh, India & Research Scholar, Sathyabama University, Chennai, India
  • R. Seshasayanan Associate Professor, Department of ECE, Anna University, Chennai, India

DOI:

https://doi.org/10.51983/ajcst-2019.8.S3.2110

Keywords:

Anti logarithmic Converter, Logarithmic Number System (LNS), Efficient FPGA, Shift-And-Add Operation

Abstract

Logarithmic conversion is a significant portion of numerous digital signals processing system and other applications. The anti logarithmic transformation presented in this paper is able to support the anti logarithmic conversion of data with the number of bits up to thirty-two. An efficient FPGA hardware implementation of logarithmic operations is an alternative option used in arithmetic operations. In this paper, we implemented an efficient anti logarithmic converter using FPGA. This implementation is compared with 28 regions error correction scheme. The proposed hardware architecture having less area, delay with less error cost. This design is implemented using HDL tool and synthesized using Xilinx CAD tool. The implementation has with respect to existing antilog converter.

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Published

24-04-2019

How to Cite

Kishore Kumar, A. T. A., & Seshasayanan, R. (2019). Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction Scheme. Asian Journal of Computer Science and Technology, 8(S3), 25–29. https://doi.org/10.51983/ajcst-2019.8.S3.2110