FFT/IFFT Processor for Ultra Wide Band Application
DOI:
https://doi.org/10.51983/ajcst-2014.3.1.1728Keywords:
Fast Fourier transform (FFT), orthogonal frequency division multiplexing (OFDM), ultra wideband (UWB)Abstract
In this paper, a novel 128-Point FFT/IFFT processor for OFDM-based UWB system has been proposed. In proposed MRMDF (Mixed Radix Multipath Delayed Feedback) architecture, high throughput rate can be achieved by using four data paths. Furthermore, the hardware costs of memory and complex multiplier can be saved by adopting delay feedback and data scheduling approaches. In addition, the number of complex multiplications is reduced effectively by using a higher radix algorithm. The measurement results show that the throughput rate of this test chip is up to 1Gsample/s while it dissipates 175mW. When the throughput rate of our processor meets UWB standard, it only consumes 77.6 mW and multiplexers. The features of the proposed MRMDF architecture are the following:
• Higher throughput rate can be provided by using four parallel data paths;
• The minimum memory is required by using the delay feedback approach to reorder the input data and the intermediate results of each module.
• The 128-point mixed-radix FFT/IFFT algorithm is implemented to power consumption.
• The number of complex multiplier is minimized by using the scheduling scheme and the specified constant multipliers.
References
A. Batraet et. al., “Multi-Band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a,” IEEE P802.15-03/268r3, Mar. 2004.
S. Magar, S. Shen, G. Luikuo, M. Fleming, and R. Aguilar, “An application specific DSP chip set for 100 MHz data rates,” in Proc. Int.Conf. Acoustics, Speech, and Signal Processing, vol. 4, Apr. 1988, pp.1989–1992.
S. He and M. Torkelson, “Designing pieline FFT processor for OFDM (de)modulation,” in Proc. URSI Int. Symp. Signals, Systems, and Electronics, vol. 29, Oct. 1998, pp. 257–262.
J. O’Brien, J. Mather, and B. Holland, “A 200 MIPS single-chip 1 k FFT processor,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol.36, 1989, pp.
B. M. Bass, “A low-power, high-performance, 1024-point FFT processor,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 380– 387, Mar.1999.
L. R. Rabiner and B. Gold, Theory and Application of Digital SignalProcessing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
J. Garcia, J. A. Michel, and A. M. Burón, “VLSI configurable delay Commutation for a pipeline split radix FFT architecture,” IEEE Trans.SignalProcess. vol. 47, no. 11, pp. 3098–3107, Nov. 1999.
W.-C. Yeh and C.-W. Jen, “High-speed and low-power split-radix FFT,” IEEE Trans. Acoust., Speech, Signal Process, vol. 51, no. 3, pp.864–874, Mar. 2003.
L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “A new VLSI-oriented FFT Algorithm and implement,” in Proc. IEEE Int. ASIC Conf., Sep. 1998, pp. 337–341.
K. Maharatna, E. Grass, and U. Jagdhold, “A 64-point fourier transform Chip for high-speed wireless lan application using OFDM,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 484–493, Mar. 2004.
Y. Jung, H. Yoon, and J. Kim, “New efficient FFT algorithm and Pipeline implementation results for OFDM/DM Tapplications,” IEEETrans.Consum. Electron., vol. 49, no. 1, pp. 14–20, Feb. 2003.
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2014 The Research Publication
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
